IRIS
PALUMBO, Francesca
 Distribuzione geografica
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Continente #
NA - Nord America 3.294
AS - Asia 2.087
SA - Sud America 1.520
EU - Europa 1.425
AF - Africa 109
OC - Oceania 6
Continente sconosciuto - Info sul continente non disponibili 4
Totale 8.445
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Nazione #
US - Stati Uniti d'America 3.174
BR - Brasile 1.380
SG - Singapore 994
CN - Cina 602
UA - Ucraina 423
DE - Germania 246
SE - Svezia 218
IT - Italia 162
HK - Hong Kong 145
GB - Regno Unito 72
CA - Canada 69
FI - Finlandia 65
VN - Vietnam 63
AR - Argentina 58
RU - Federazione Russa 49
KR - Corea 41
FR - Francia 36
MX - Messico 34
ZA - Sudafrica 32
IN - India 31
BD - Bangladesh 29
MA - Marocco 28
TR - Turchia 28
BE - Belgio 27
IQ - Iraq 26
EC - Ecuador 23
LT - Lituania 22
CZ - Repubblica Ceca 21
ES - Italia 17
PL - Polonia 17
CO - Colombia 15
UZ - Uzbekistan 15
KE - Kenya 14
VE - Venezuela 14
AZ - Azerbaigian 12
JO - Giordania 12
JP - Giappone 12
NL - Olanda 12
AT - Austria 9
DZ - Algeria 9
PK - Pakistan 9
NP - Nepal 8
PY - Paraguay 8
TN - Tunisia 8
CL - Cile 7
GE - Georgia 7
RO - Romania 7
AE - Emirati Arabi Uniti 6
KG - Kirghizistan 6
SA - Arabia Saudita 6
AU - Australia 5
ID - Indonesia 5
IL - Israele 5
PE - Perù 5
UY - Uruguay 5
BO - Bolivia 4
EG - Egitto 4
GR - Grecia 4
JM - Giamaica 4
KZ - Kazakistan 4
OM - Oman 4
SN - Senegal 4
AL - Albania 3
BN - Brunei Darussalam 3
HN - Honduras 3
PA - Panama 3
BG - Bulgaria 2
BY - Bielorussia 2
CI - Costa d'Avorio 2
CR - Costa Rica 2
DO - Repubblica Dominicana 2
GA - Gabon 2
HU - Ungheria 2
KW - Kuwait 2
MY - Malesia 2
QA - Qatar 2
RS - Serbia 2
XK - ???statistics.table.value.countryCode.XK??? 2
A2 - ???statistics.table.value.countryCode.A2??? 1
AM - Armenia 1
AO - Angola 1
BA - Bosnia-Erzegovina 1
BW - Botswana 1
CH - Svizzera 1
DK - Danimarca 1
EE - Estonia 1
ET - Etiopia 1
EU - Europa 1
GY - Guiana 1
HR - Croazia 1
IE - Irlanda 1
IM - Isola di Man 1
IR - Iran 1
LB - Libano 1
LK - Sri Lanka 1
ML - Mali 1
MN - Mongolia 1
NG - Nigeria 1
NI - Nicaragua 1
NZ - Nuova Zelanda 1
Totale 8.439
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Città #
Dallas 989
Singapore 521
Chandler 398
Jacksonville 255
Beijing 188
Princeton 154
Hong Kong 144
Ashburn 143
São Paulo 99
New York 88
Dearborn 86
Nanjing 81
Ann Arbor 71
Shanghai 58
Wilmington 53
Los Angeles 48
Belo Horizonte 43
Seoul 40
Rio de Janeiro 39
Munich 38
Nanchang 35
Boardman 27
Brussels 27
Santa Clara 27
Toronto 27
Brasília 26
Milan 26
Tianjin 25
Council Bluffs 24
Mountain View 23
Sassari 23
Brooklyn 21
Columbus 21
Brno 20
Jiaxing 20
Johannesburg 20
Montreal 19
Porto Alegre 19
Frankfurt am Main 18
Hanoi 18
The Dalles 18
Curitiba 17
Ho Chi Minh City 17
Warsaw 17
Changsha 16
Hebei 16
Helsinki 16
San Francisco 16
Cagliari 15
Guangzhou 15
Shenyang 15
Fortaleza 14
Guarulhos 14
Tashkent 14
Jinan 13
London 13
Manaus 13
Nairobi 13
Ottawa 13
Rome 13
Campinas 12
Norwalk 12
Zhengzhou 12
Amman 11
Baku 11
Contagem 11
Houston 11
Juiz de Fora 11
Ningbo 11
Salvador 11
Tokyo 11
Bologna 10
Casablanca 10
Caxias do Sul 10
Chennai 10
Denver 10
Joinville 10
Quito 10
São José dos Campos 10
Baghdad 9
Düsseldorf 9
Kunming 9
Mexico City 9
Osasco 9
Ribeirão Preto 9
Várzea Paulista 9
Amsterdam 8
Atlanta 8
Da Nang 8
Goiânia 8
Istanbul 8
Orem 8
Phoenix 8
Poplar 8
Stockholm 8
São José 8
Bogotá 7
Boston 7
Maringá 7
Mumbai 7
Totale 4.675
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Nome #
Adaptable AES implementation with power-gating support 152
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project 147
Adaptive software-augmented hardware reconfiguration with dataflow design automation 142
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case 138
A Novel Non-Exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs 137
Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units 137
Hardware/Software self-adaptation in CPS: The CERBERO project approach 137
A nature-inspired adaptive floating-point coprocessing system 137
CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments 136
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations 133
Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA 131
Preface 128
The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design 128
Automated Design Flow for Multi-Functional Dataflow-Based Platforms 127
In-Field Automatic Detection of Grape Bunches under a Totally Uncontrolled Environment 127
Automated power gating methodology for dataflow-based reconfigurable systems 126
A coarse-grained reconfigurable approach for low-power spike sorting architectures 124
ALOHA: An architectural-aware framework for deep learning at the edge 123
Power and clock gating modelling in coarse grained reconfigurable systems 120
Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators 120
An FPGA platform for real-time simulation of spiking neuronal networks 119
Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project 119
A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool 118
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching 116
Demo: Reconfigurable Platform Composer Tool 115
Power Modelling for Saving Strategies in Coarse Grained Reconfigurable Systems 112
An integrated hardware/software design methodology for signal processing systems 110
A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC 110
A Composable Monitoring System for Heterogeneous Embedded Platforms 109
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation 109
Optimization and deployment of CNNs at the Edge: The ALOHA experience 108
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy 106
FPGA-based Implementation for Industrial Motion Control System 105
Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy 104
RVC: A multi-decoder CAL Composer tool 104
NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning 103
Feasibility study of real-time spiking neural network simulations on a swarm intelligence based digital architecture 103
Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI 102
A surface tension and coalescence model for dynamic distributed resources allocation in Massively Parallel Processors on-Chip 101
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 99
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing 98
Hardware design methodology using lightweight dataflow and its integration with low power techniques 98
Towards self-adaptive networks on chip for massively parallel processors: Multilevel quality of service programmability 96
Elicitation of technical requirements in large research projects: The CERBERO approach 96
Cross-layer design of reconfigurable cyber-physical systems 96
SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract 94
Non-Exclusive Dual-Mode Approach for NoC Designs 93
Coarse-Grained Reconfigurable Approach for Multi-Dataflow Systems 92
Low power design methodology for signal processing systems using lightweight dataflow techniques 90
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project 90
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding 89
Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures 89
sysCgrid: SystemC grid simulation framework 88
Message from the General Chairs 86
Coarse-grained reconfiguration: dataflow-based power management 85
Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding 85
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain 84
Multi-purpose systems: A novel dataflow-based generation and mapping strategy 82
DSE and profiling of multi-context coarse-grained reconfigurable systems 81
Exploring the performance of partially reconfigurable point-to-point interconnects 80
PathTracer: Understanding Response Time of Signal Processing Applications on Heterogeneous MPSoCs 80
Profiling of Dataflow-Based Coarse-Grained Reconfigurable Platforms 79
Challenging CPS trade-off adaptivity with coarse-grained reconfiguration 76
Dataflow modeling for reconfigurable signal processing systems 76
Message from the Program Chairs 76
Multi-grain reconfiguration for advanced adaptivity in cyber-physical systems 76
Design IP Faster: Introducing the C~ High-Level Language 75
Neu Pow: Artificial Neural Networks for Power and Behavioral Modeling of Arithmetic Components in 45nm ASICs Technology 75
Introduction to the 2nd workshop on design of low Power EMbedded Systems 73
Impact of half-duplex and full-duplex DMA Implementations on NoC performance 73
Computing Swarms for Self-Adaptiveness and Self-Organization in Floating Point Array Processing 71
Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC 71
PathTracing: Raising the level of understanding of processing latency in heterogeneous MPSoCs 70
Editorial: Special Issue on Computing Frontiers 70
The multi-dataflow composer tool: A runtime reconfigurable HDL platform composer 69
The FitOptiVis ECSEL Project: Highly Efficient Distributed Embedded Image/Video Processing in Cyber-Physical Systems Invited Pape 69
Front Matter, Table of Contents, Preface, Conference Organization 68
MYRTUS: Multi-layer 360° dYnamic orchestration and interopeRable design environmenT for compute-continUum Systems 68
Multithread Accelerators on FPGAs: A Dataflow-Based Approach 66
Reconfigurable and approximate computing for video coding 65
On-the-fly adaptivity for process networks over shared-memory platforms 61
Preface to the Special Issue on Methods, Tools, and Architectures for Signal and Image Processing 61
Hybrid switching techniques for heterogeneous traffic support in multi-processors system on chip and massively parallel processors 61
Concurrent hybrid switching for massively parallel systems-on-chip: The CYBER architecture 60
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms 59
SECURED for Health: Scaling Up Privacy to Enable the Integration of the European Health Data Space 58
Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design 54
Unmanned vehicles in smart farming: A survey and a glance at future horizons 51
Preface 49
Totale 8.574
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Categoria #
all - tutte 35.592
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 35.592
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021393 0 0 0 0 0 46 79 22 81 107 25 33
2021/2022350 53 5 1 3 3 1 6 27 22 26 42 161
2022/2023834 83 23 25 111 91 129 45 107 148 5 41 26
2023/2024327 48 24 5 7 52 55 0 19 0 6 54 57
2024/20253.037 29 12 144 73 181 160 160 652 1.108 334 140 44
2025/20262.397 176 879 292 571 371 108 0 0 0 0 0 0
Totale 8.574