Applications and hardware complexity management in modern systems tend to collide with efficient resource and power balance. Therefore, dedicated and power-aware design frameworks are necessary to implement efficient multi-functional runtime reconfigurable signal processing platforms. In this work, we adopt dataflow specifications as a starting point to challenge power minimization.

Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy / Palumbo, Francesca; Sau, C; Raffo, L.. - (2014), pp. 1-6. (Intervento presentato al convegno 2014 IEEE International Workshop on Signal Processing Systems tenutosi a Belfast (Regno Unito) nel 20-22 October 2014) [10.1109/SiPS.2014.6986104].

Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy

PALUMBO, Francesca;
2014-01-01

Abstract

Applications and hardware complexity management in modern systems tend to collide with efficient resource and power balance. Therefore, dedicated and power-aware design frameworks are necessary to implement efficient multi-functional runtime reconfigurable signal processing platforms. In this work, we adopt dataflow specifications as a starting point to challenge power minimization.
2014
Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy / Palumbo, Francesca; Sau, C; Raffo, L.. - (2014), pp. 1-6. (Intervento presentato al convegno 2014 IEEE International Workshop on Signal Processing Systems tenutosi a Belfast (Regno Unito) nel 20-22 October 2014) [10.1109/SiPS.2014.6986104].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11388/144856
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