Multi-Processors System on Chip (MPSoCs) and Massively Parallel Processors (MPPs) architectures are conceived to efficiently implement Thread Level Parallelism, a common characteristic of modern software applications targeted by embedded systems. Each core in a MPP environment is designed to execute a particular instructions flow, known as thread, in a completely self-sufficient manner, being able to communicate with the other cores in order to exchange shared data. The demand of parallelism in MPPs and MPSoCs entails the design of an efficient communication layer able to sustain it. This means that the interconnection medium has to be both scalable, to allow multiple accesses of the different cores to the shared resources, and optimized in terms of wiring. These are all native characteristics of Networks on Chip (NoCs). In MPSoCs and MPPs, it is necessary to provide: - a quick resolution of the interdependencies among different threads, single scalar data or even vectors. Interdependencies are responsible of completion time delay because prevent a thread from completion when not resolved; - load balancing support techniques to avoid hot spots and to efficiently exploit all the cores available on chip. When threads migration occurs, a regular and continuous traffic is generated, made up of long streams of data; - management of end-to-end small control data. Circuit Switching (CS) technique is the method by which a dedicated path, or circuit, is established prior the sending of the sensitive data. Circuit switched networks are suitable for guaranteed throughput applications, especially in case of real time communications. In Packet Switching (PS) methodologies the intermediate routers are responsible for routing the individual packets through the network, neither following a predefined nor a reserved path. Packet switched networks are suitable for best-effort services or for soft-timing constrained communications. In this chapter we will look at the possibility of combining CS and PS in order to support the heterogeneous traffic patterns coexisting in a MPP environment. Hybrid switching networks are designed to guarantee the benefits of both CS and PS consisting in a better usage of the available bandwidth and in a global increase of the overall throughput, at the price of a more complex hardware implementation. In this scope, the latest approaches in literature are presented, together with a particular NoC model able to provide dual-mode hybrid switching in a non-exclusive way, intended as the possibility of co-sharing the amount of available bandwidth between CS and PS communications.

Hybrid switching techniques for heterogeneous traffic support in multi-processors system on chip and massively parallel processors / Palumbo, Francesca; Pani, D; Raffo, L.. - (2011), pp. 301-339.

Hybrid switching techniques for heterogeneous traffic support in multi-processors system on chip and massively parallel processors

PALUMBO, Francesca;
2011-01-01

Abstract

Multi-Processors System on Chip (MPSoCs) and Massively Parallel Processors (MPPs) architectures are conceived to efficiently implement Thread Level Parallelism, a common characteristic of modern software applications targeted by embedded systems. Each core in a MPP environment is designed to execute a particular instructions flow, known as thread, in a completely self-sufficient manner, being able to communicate with the other cores in order to exchange shared data. The demand of parallelism in MPPs and MPSoCs entails the design of an efficient communication layer able to sustain it. This means that the interconnection medium has to be both scalable, to allow multiple accesses of the different cores to the shared resources, and optimized in terms of wiring. These are all native characteristics of Networks on Chip (NoCs). In MPSoCs and MPPs, it is necessary to provide: - a quick resolution of the interdependencies among different threads, single scalar data or even vectors. Interdependencies are responsible of completion time delay because prevent a thread from completion when not resolved; - load balancing support techniques to avoid hot spots and to efficiently exploit all the cores available on chip. When threads migration occurs, a regular and continuous traffic is generated, made up of long streams of data; - management of end-to-end small control data. Circuit Switching (CS) technique is the method by which a dedicated path, or circuit, is established prior the sending of the sensitive data. Circuit switched networks are suitable for guaranteed throughput applications, especially in case of real time communications. In Packet Switching (PS) methodologies the intermediate routers are responsible for routing the individual packets through the network, neither following a predefined nor a reserved path. Packet switched networks are suitable for best-effort services or for soft-timing constrained communications. In this chapter we will look at the possibility of combining CS and PS in order to support the heterogeneous traffic patterns coexisting in a MPP environment. Hybrid switching networks are designed to guarantee the benefits of both CS and PS consisting in a better usage of the available bandwidth and in a global increase of the overall throughput, at the price of a more complex hardware implementation. In this scope, the latest approaches in literature are presented, together with a particular NoC model able to provide dual-mode hybrid switching in a non-exclusive way, intended as the possibility of co-sharing the amount of available bandwidth between CS and PS communications.
2011
978-161728730-5
Hybrid switching techniques for heterogeneous traffic support in multi-processors system on chip and massively parallel processors / Palumbo, Francesca; Pani, D; Raffo, L.. - (2011), pp. 301-339.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11388/146979
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