As the multi-core processors era took place, several design concerns have risen. Interconnection layer efficiency has gained particular relevance as a crucial issue to be addressed in order to leverage the large amount of on-chip resources that today’s VLSI technologies are able to provide. At the same time, as the architectural parallelism will continue to grow and become more fine-grained, the kind of traffic generated by the different multithreaded applications is turning out to be very wide-ranging in terms of size and burstiness. In order to adapt to this large variety of traf- fic to be supported, several models of dual-mode routers have been developed, implementing both packet switching and circuit switching techniques, thus supporting both best effort and guaranteed throughput services. This paper introduces an innovative model of non-exclusive dual-mode router, able to combine the aforementioned features in a non exclusive way (i.e.: in parallel inside the network on the same link). This feature makes this NoC architecture well-suited for Multi-Processor System on-Chip (MPSoC) architectures with a high level of parallelism which have to deal with heterogeneous traffic conditions, such as Massively Parallel Processors (MPPs) and Processor Arrays (PAs).
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching / Secchi, S; Palumbo, Francesca; Pani, D; Raffo, L.. - P3277:(2008), pp. 141-148. (Intervento presentato al convegno EUROMICRO Conference on Digital System Design (DSD 2008) tenutosi a Parma, ITALY nel September 3-5, 2008) [10.1109/DSD.2008.64].
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching
PALUMBO, Francesca;
2008-01-01
Abstract
As the multi-core processors era took place, several design concerns have risen. Interconnection layer efficiency has gained particular relevance as a crucial issue to be addressed in order to leverage the large amount of on-chip resources that today’s VLSI technologies are able to provide. At the same time, as the architectural parallelism will continue to grow and become more fine-grained, the kind of traffic generated by the different multithreaded applications is turning out to be very wide-ranging in terms of size and burstiness. In order to adapt to this large variety of traf- fic to be supported, several models of dual-mode routers have been developed, implementing both packet switching and circuit switching techniques, thus supporting both best effort and guaranteed throughput services. This paper introduces an innovative model of non-exclusive dual-mode router, able to combine the aforementioned features in a non exclusive way (i.e.: in parallel inside the network on the same link). This feature makes this NoC architecture well-suited for Multi-Processor System on-Chip (MPSoC) architectures with a high level of parallelism which have to deal with heterogeneous traffic conditions, such as Massively Parallel Processors (MPPs) and Processor Arrays (PAs).I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
