This paper presents a novel Network on Chip able to offer flexibility to multi-threaded heterogeneous traffic applications typical of massive multicore chips. It combines different switching types and data control flow protocols, allowing to reprogram on the fly the total amount of bandwidth available per switching type. In principle this can be easily performed in runtime by the introduction of simple smart hardware performance counters in order to automatically improve the quality of service
Towards self-adaptive networks on chip for massively parallel processors: Multilevel quality of service programmability / Palumbo, Francesca; Pani, D; Deidda, A; Raffo, L.. - (2011), pp. 1-2. (Intervento presentato al convegno 8th ACM International Conference on Computing Frontiers, CF'11 tenutosi a Ischia, Italy nel 3-5/5/2011) [10.1145/2016604.2016627].
Towards self-adaptive networks on chip for massively parallel processors: Multilevel quality of service programmability
PALUMBO, Francesca;
2011-01-01
Abstract
This paper presents a novel Network on Chip able to offer flexibility to multi-threaded heterogeneous traffic applications typical of massive multicore chips. It combines different switching types and data control flow protocols, allowing to reprogram on the fly the total amount of bandwidth available per switching type. In principle this can be easily performed in runtime by the introduction of simple smart hardware performance counters in order to automatically improve the quality of serviceI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
