Flexibility and high efficiency are common design drivers in the embedded systems domain. Coarse-grained recon- figurable coprocessors can tackle these issues, but they suffer of complex design, debugging and applications mapping problems. In this paper, we propose an automated design flow that aids developers in design and managing coarse-grained reconfigurable coprocessors. It provides both the hardware IP and the software drivers, featuring two different levels of coupling with the host processor. The presented solution has been tested on a JPEG codec, targeting a commercial Xilinx Virtex-5 FPGA.
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain / Sau, C; Fanni, L; Meloni, P; Raffo, L; Palumbo, Francesca. - (2015), pp. 1-8. (Intervento presentato al convegno Reconfigurable Computing and FPGAs tenutosi a Cancun (MEX) nel 7-9 Dicembre) [10.1109/ReConFig.2015.7393351].
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain
PALUMBO, FrancescaSupervision
2015-01-01
Abstract
Flexibility and high efficiency are common design drivers in the embedded systems domain. Coarse-grained recon- figurable coprocessors can tackle these issues, but they suffer of complex design, debugging and applications mapping problems. In this paper, we propose an automated design flow that aids developers in design and managing coarse-grained reconfigurable coprocessors. It provides both the hardware IP and the software drivers, featuring two different levels of coupling with the host processor. The presented solution has been tested on a JPEG codec, targeting a commercial Xilinx Virtex-5 FPGA.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
