The manual creation of specialized hard-ware infrastructures for complex multi-purpose systems is error-prone and time-consuming. Moreover, lots of effort is required to define an optimized and heterogeneous components library. To tackle these issues, we propose a novel design flow based on the Dataflow Process Networks Model of Computation. In particular, we have combined the operation of two state of the art tools, the Multi-Dataflow Composer and the Open RVC-CAL Compiler, handling respectively the automatic mapping of a reconfigurable multi-purpose substrate and the high level synthesis of hardware components. Our approach guarantees runtime efficiency and on-chip area saving both on FPGAs and ASICs.
Multi-purpose systems: A novel dataflow-based generation and mapping strategy / Nezan, Jf; Siret, N; Wipliez, M; Palumbo, Francesca; Raffo, L.. - (2012), pp. 1-4. (Intervento presentato al convegno 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 tenutosi a Seoul South Korea nel 20-23/05/2012) [10.1109/ISCAS.2012.6271969].
Multi-purpose systems: A novel dataflow-based generation and mapping strategy
PALUMBO, Francesca;
2012-01-01
Abstract
The manual creation of specialized hard-ware infrastructures for complex multi-purpose systems is error-prone and time-consuming. Moreover, lots of effort is required to define an optimized and heterogeneous components library. To tackle these issues, we propose a novel design flow based on the Dataflow Process Networks Model of Computation. In particular, we have combined the operation of two state of the art tools, the Multi-Dataflow Composer and the Open RVC-CAL Compiler, handling respectively the automatic mapping of a reconfigurable multi-purpose substrate and the high level synthesis of hardware components. Our approach guarantees runtime efficiency and on-chip area saving both on FPGAs and ASICs.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
