Applicable in different fields and markets, low energy high efficiency video coding (HEVC) codecs and their constituting elements have been heavily studied. Fractional pixel interpolation is one of its most costly blocks. In this letter, a field programmable gate array implementation of HEVC fractional pixel interpolation, outperforming literature solutions, is proposed. Approximate computing, in conjunction with hardware reconfiguration, guarantees a tunable interpolation system offering an energy versus quality tradeoff to further reduce energy.
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing / Sau, C., Palumbo, F., Pelcat, M., Heulot, J., Nogues, E., Menard, D., Meloni, P., Raffo, L.. - In: IEEE EMBEDDED SYSTEMS LETTERS. - ISSN 1943-0663. - 9:3(2017), pp. 65-68. [10.1109/LES.2017.2703585]
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing
PALUMBO, Francesca;MELONI, Paolo;RAFFO, Luigi
2017-01-01
Abstract
Applicable in different fields and markets, low energy high efficiency video coding (HEVC) codecs and their constituting elements have been heavily studied. Fractional pixel interpolation is one of its most costly blocks. In this letter, a field programmable gate array implementation of HEVC fractional pixel interpolation, outperforming literature solutions, is proposed. Approximate computing, in conjunction with hardware reconfiguration, guarantees a tunable interpolation system offering an energy versus quality tradeoff to further reduce energy.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
