statistiche ricercatore

Nome	#
Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators	61
Adaptive software-augmented hardware reconfiguration with dataflow design automation	61
Hardware/Software self-adaptation in CPS: The CERBERO project approach	46
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation	45
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs	45
The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design	40
Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA	38
A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC	30
Edge-to-Cloud Continuum Orchestrator for Distributed Video Applications	16
PathTracer: Understanding Response Time of Signal Processing Applications on Heterogeneous MPSoCs	16
Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI	15
FPGA-based Implementation for Industrial Motion Control System	8
A Custom dual-processor System for Real-time Neural Signal Processing	8
A low-overhead AXI bridge on SpaceWire for multi-device spacecraft systems	8
Extending architecture modeling for signal processing towards GPUs	7
PathTracing: Raising the level of understanding of processing latency in heterogeneous MPSoCs	7
Dataflow-based adaptation framework with coarse-grained reconfigurable accelerators	6
Totale	457

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2019/2020	17	0	0	0	0	4	0	4	0	4	1	4	0
2020/2021	59	4	0	6	0	12	4	8	5	9	9	1	1
2021/2022	36	2	0	0	1	2	0	1	8	1	4	2	15
2022/2023	112	9	3	2	17	11	13	9	13	20	2	8	5
2023/2024	68	3	3	1	1	13	8	0	19	0	1	14	5
2024/2025	135	9	3	61	24	38	0	0	0	0	0	0	0
Totale													457