Power reduction is one of the biggest challenges in modern systems and tends to become a severe issue dealing with complex scenarios. To provide high-performance and exibility, designers often opt for coarse-grained reconfigurable (CGR) systems. Nevertheless, these systems require specific attention to the power problem, since large set of resources may be underutilized while computing a certain task. This paper focuses on this issue. Targeting CGR devices, we propose a way to model in advance power and clock gating costs on the basis of the functional, technological and architectural parameters of the baseline CGR system. The proposed flow guides designers towards optimal implementations, saving designer effort and time.
Power and clock gating modelling in coarse grained reconfigurable systems / Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca. - (2016), pp. 384-391. (Intervento presentato al convegno ACM International Conference on Computing Frontiers, CF 2016 tenutosi a ita nel 2016) [10.1145/2903150.2911713].
Power and clock gating modelling in coarse grained reconfigurable systems
MELONI, Paolo;PALUMBO, Francesca
2016-01-01
Abstract
Power reduction is one of the biggest challenges in modern systems and tends to become a severe issue dealing with complex scenarios. To provide high-performance and exibility, designers often opt for coarse-grained reconfigurable (CGR) systems. Nevertheless, these systems require specific attention to the power problem, since large set of resources may be underutilized while computing a certain task. This paper focuses on this issue. Targeting CGR devices, we propose a way to model in advance power and clock gating costs on the basis of the functional, technological and architectural parameters of the baseline CGR system. The proposed flow guides designers towards optimal implementations, saving designer effort and time.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.