Sfoglia per Autore
Non-Exclusive Dual-Mode Approach for NoC Designs
2008-01-01 Palumbo, Francesca; Secchi, S; Pani, D; Raffo, L.
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching
2008-01-01 Secchi, S; Palumbo, Francesca; Pani, D; Raffo, L.
A Novel Non-Exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs
2008-01-01 Palumbo, Francesca; Secchi, S; Pani, D; Raffo, L.
A surface tension and coalescence model for dynamic distributed resources allocation in Massively Parallel Processors on-Chip
2008-01-01 Palumbo, Francesca; Pani, D; Raffo, L; Secchi, S.
sysCgrid: SystemC grid simulation framework
2009-01-01 Palumbo, Francesca; Pani, D; Raffo, L.
RVC: A multi-decoder CAL Composer tool
2010-01-01 Palumbo, Francesca; Pani, D; Manca, E; Raffo, L; Mattavelli, M; Roquier, G.
Impact of half-duplex and full-duplex DMA Implementations on NoC performance
2010-01-01 Palumbo, Francesca; Pani, D; Pilia, A; Raffo, L.
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations
2010-01-01 Pani, D; Palumbo, Francesca; Raffo, L.
Coarse-Grained Reconfigurable Approach for Multi-Dataflow Systems
2011-01-01 Carta, N; Palumbo, Francesca; Raffo, L.
Towards self-adaptive networks on chip for massively parallel processors: Multilevel quality of service programmability
2011-01-01 Palumbo, Francesca; Pani, D; Deidda, A; Raffo, L.
Hybrid switching techniques for heterogeneous traffic support in multi-processors system on chip and massively parallel processors
2011-01-01 Palumbo, Francesca; Pani, D; Raffo, L.
The multi-dataflow composer tool: A runtime reconfigurable HDL platform composer
2011-01-01 Palumbo, Francesca; Carta, N; Raffo, L.
Design IP Faster: Introducing the C~ High-Level Language
2012-01-01 Wipliez, M; Siret, N; Carta, N; Palumbo, Francesca; Raffo, L.
Multi-purpose systems: A novel dataflow-based generation and mapping strategy
2012-01-01 Nezan, Jf; Siret, N; Wipliez, M; Palumbo, Francesca; Raffo, L.
A nature-inspired adaptive floating-point coprocessing system
2012-01-01 Sau, C; Pani, D; Palumbo, Francesca; Raffo, L.
Concurrent hybrid switching for massively parallel systems-on-chip: The CYBER architecture
2012-01-01 Palumbo, Francesca; Pani, D; Congiu, A; Raffo, L.
Profiling of Dataflow-Based Coarse-Grained Reconfigurable Platforms
2013-01-01 Sau, C; Palumbo, Francesca; Raffo, L.
DSE and profiling of multi-context coarse-grained reconfigurable systems
2013-01-01 Palumbo, Francesca; Sau, C; Raffo, L.
A coarse-grained reconfigurable approach for low-power spike sorting architectures
2013-01-01 Carta, N; Sau, C; Pani, D; Palumbo, Francesca; Raffo, L.
A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool
2013-01-01 Carta, N; Sau, C; Palumbo, Francesca; Pani, D; Raffo, L.
Legenda icone
- file ad accesso aperto
- file disponibili sulla rete interna
- file disponibili agli utenti autorizzati
- file disponibili solo agli amministratori
- file sotto embargo
- nessun file disponibile